Makefile tutorial:
==================

Review: 
=======================================================
- compiling a file means turning it into an object file.
- linking means taking several object files and creating an executeable.
- build is the process of taking source files and creating an executeable 
  - (ie compiling then linking).


Here is the what a build looks like in psuedo commands:
=======================================================
source1.c --COMPILE--> obj1.o
source2.c --COMPILE--> obj2.o

obj1.o obj2.o --LINK--> executeable

- This process can be rather tedious. We can automate it using a make file.
- "make" is a program in Unix that can be called by simply typing "make" in the command line.
- typing "make" tells the system to look for and run a file called "Makefile" in the current directory.
- in short, Makefiles are used to compile and link several files.


A makefile is comprised of a set of rules.
=======================================================
Each rule executes a command, such as create a file. Here is the syntax of a rule:

output_file : input_file input_file
  action
  action
  
(where the input_files can be thought of as "dependencies")
('input_file' can be either a source file or an object file)
  
Example:
*****************************************
* # Create executeable file 'client'    *  comments start with '#'
* client: conn.o                        *
* <tab> g++ client.cpp conn.o -o client *  note that each "action" 
*                                       *  line must start with a tab
* # Create object file 'conn.o          *
* conn.o: conn.cpp conn.h               *
* <tab> g++ -c conn.cpp -o conn.o       *  don't type "<tab>"
*****************************************

Here is what the above makefile does:
- it generates an executeable called client
- it uses the g++ compiler to create an object file conn.o
- conn.o is created from the source files conn.cpp and conn.h

Variables:
=======================================================
Define a variable:
$VAR_NAME=value

Example:
*************************** by convention, variables are UPPERCASE
* $CC = main.o test.o     * declare & define a variable
* CC = gcc                * assign gcc to cc (overwrites main.o test.o)
* CC += -o                * append '-o', resulting in CC = "gcc -o"
*************************** 

You can get a variable's value with the following syntax:
$(VAR_NAME)


The special 'all' keyword:
=======================================================
all is the default target and is called when "make" is run from the terminal with no options.

Example:
***************************
* all: myprog1 myprog2    * 
*************************** 

Running "make" will build both myprog1 and myprog2.


Advanced Variables:
=======================================================
Wildcard operator: %

%.o will match any .o file (ie, any object file)
%.c will match any .c file (ie, any c source file)
$@ will match the output_file in the line above it.
$< will match the input_files in the line above it.

Example:
******************
* main.o: main.c *
*   gcc-o $@ $<  *
******************

In the above case,
$@ will be replace with main.o, and 
$< will be replaced with main.cpp.

Further Reading:
http://www.metalshell.com/view/tutorial/120/